Embodiments of the present invention relate generally to a method and system for performing data decimation, and more particularly for decimating along at least one dimension of an array of video pixels in a video processing system and/or graphics subsystem.
Decimation of a frame of pixels to scale the frame is a common function in a video processing system. In particular, decimation along the horizontal dimension of the frame is often performed.
Typically, the decimation function is performed in hardware using a digital filter to effectively collapse groups of two or more pixels, along the horizontal dimension of the frame of pixels, into a single pixel per group. The digital filter is often implemented using hardware elements such as multipliers, adders, and multiplexers.
For example, a 2-tap digital filter is commonly used to average pairs of pixels to accomplish 2-to-1 decimation. Such traditional hardware implementations may be inflexible and limit the types of decimation that may be performed and the types of video formats that may be used such as, for example, the YUVA digital video format.
It is desirable to have a more flexible, programmable architecture that may handle many types of decimation formats including integer decimation, non-integer decimation, simple averaging, complex digital filtering, etc.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with embodiments of the present invention as set forth in the remainder of the present application with reference to the drawings.